SOLUTION TO CHALLENGE OF THE WEEK – 5

1.  Identify the digital circuit and write its truth table.

Note: Here V1 and V2 are the input signals and O1 and O2 are the output signals.

Solution:

Case 1: Assume V1=5V, V2=0V

When V1 is 5V, the transistor Q1 is turned ON and hence output O1 = 0V. Also V2=0V, turns OFF the transistor Q2, giving O2=5V.

 Case 2: Assume V1=0V, V2=5V

When V1 is 0V, the transistor Q1 is turned OFF and hence output O1 = 5V. Also V2=5V, turns ON the transistor Q2, giving O2=0V.

Case 3: Assume V1=0V, V2=0V

Since both the inputs are 0V, the outputs cross-connected to base of opposite transistors act as input. Hence if O1 is 5V, the transistor Q2 is turned ON and hence output O2 = 0V. Now since O2=0V, the transistor Q1 turns OFF, giving O1=5V.

Case 4: Assume V1=5V, V2=5V

In this case both the inputs are high, and hence both transistors try turning ON and maintain their outputs O1 and O2 low.

The above 4 cases are equivalent to an SR latch. Hence the digital circuit is an SR Latch.

2. Draw the output waveform v_o for the circuit shown below with the given input. (Assume β = 100)

Solution: In the above circuit as soon as the input voltage goes higher than 5V (due to 5V Zener diode connected to the emitter), large current flows to drive the transistor into saturation region and the output switches to low state. The output voltage is restricted to 5V due to the presence of Zener diode. When the input is lower than 5V, the transistor is in cut-off region and output remains is high state, i.e., at 15V.

The output waveform is as shown below.

No winners for COTW 5.

COTW-6

1. For the RC circuit with input as shown below, draw the waveform for the voltage across the resistor. Note:  the capacitor is initially uncharged.

CHALLENGE OF THE WEEK - 5

Date : 28/10/2013

1.  Identify the digital circuit and write its truth table.

Note: Here V1 and V2 are the input signals and O1 and O2 are the output signals. Assume Vs = 5V.

2. The question given below is optional. It carries bonus point of  +1.

Draw the output waveform v_o for the circuit shown below with the given input. (Assume β = 100)

Hint: The base current will flow only when base-emitter junction of BJT is forward biased and Zener diode is reversed biased.

Last date for submission:  9/11/13

No winners for COTW - 4

CHALLENGE OF THE WEEK - 4

For all years:

Draw the output waveform v_o for the circuit shown below with the given input. (Assume β = 100)

Last date for submission: 11/10/13

Challenge of the Week -3 Solution and Winners

Winners of COTW 3

    Name                                            Total points

Aneesha J D'Souza	III Sem A	3
Anushree Shenoy	III Sem A	3
Disha Ramesh Shet	III Sem A	3
Akshaya S Palan	III Sem A	2
Jaiganesh Rane	III Sem A	1
Pooja Poojary	III Sem B	3
Priyanka Shetty	III Sem B	3
Mefil D'Souza	III Sem B	2
Mohith Prabhu M	III Sem B	2
Pratheek P B	III Sem B	2
Pallavi Bhatka S	III Sem B	2
Sukanya Pai	III Sem C	3
Suraksha  Shetty	III Sem C	3

CHALLENGE OF THE WEEK-3

Date: 21/9/13

For 2^nd years:

1.  A practical DC current source provides 20kW to a 50Ω load and the same power while load is 200Ω. What is the maximum power that can be drawn from the current source?

For 3rd  & 4th years:

In the op-amp circuit shown in the above figure , find the load current i_L?

Last date for submission: 28/9/13

CHALLENGE OF THE WEEK-2 SOLUTION AND WINNERS

SOLUTION:

Consider the first block as shown with output  as 'x'.

Assuming the drop across each diode is considered to be 0.7. 

Case 1:

 A=0, B=0

Both the diodes conduct and hence the voltage at x=0.7 i.e., equivalent to logic '0'.

Case 2:

A=0, B=1 / A=1, B=0 (logic '1' represents +5V)

Only one diode conducts while other is reverse biased. So the voltage at x=0.7 ≈ logic '0'.

Case 3:

A=1, B=1

Both the diodes are reverse biased and hence they act as open connections resulting in voltage as x=5V ≈ logic '1'.

Hence the first block is found to be behaving as an logical AND gate. Therefore x=A^.B.

Similarly considering x and C to be input to next identical connection whose output is y, we find its operation to be  similar as first block i.e., y=x^.C=A^.B^.C.

The last gate in above diagram is a logical NOT gate, hence provides complimentary output, i.e.,

Hence we infer that, the above logic circuit is a 3-input-NAND gate.  

COTW - 2 RESULTS:

NAME                                   SECTION       POINTS

Aneesha J D'Souza               III Sem A        2                                                         

Anushree Shenoy                  III Sem A        2                                                         

Disha Ramesh Shet              III Sem A        2                                                         

Abhilash                                 III Sem A        1                                                                     

Anjana R                                III Sem A        1                                                                     

Deepa S                                 III Sem A        1         

Akshaya S Palan                   III Sem A        1                                                         

Pooja Poojary                        III Sem B         2

Priyanka Shetty                    III Sem B         2

Kshetha Rainal                     III Sem B         1                                                                     

Mefil D'Souza                       III Sem B         1                                                         

Mohith Prabhu M                 III Sem B         1

Pratheek P B                         III Sem B         1

Pallavi Bhatka S                   III Sem B         1                                                                     

Shwetha                                 III Sem C         2

Sukanya Pai                          III Sem C         2

Suraksha  Shetty                  III Sem C         2

Shreshta                                  III Sem C         1

Congratulation Winners